This invention relates to a wholly digital apparatus for decoding data and timing components from an encoded Manchester II waveform.
A commonly used digital encoding technique is the Manchester II code in which data and data clock components are combined into a single encoded waveform. The encoded Manchester II waveform is divided into time units of equal duration commonly called data cells during which one binary digit (bit) of information is conveyed. The state of the bit is indicated by a transition in the waveform occurring at the center or mid-cell point of the data cell. The direction of the transition indicates the value of the bit. At least one signal transition per data cell occurs, providing a component in the frequency domain centered at the data clock rate which is twice the bit occurrence rate. The Manchester II code is also known as the biphase, phase-shift, or split-phase code.
The prior art contains a variety of circuit methods directed toward decoding Manchester-type data. Among these, three stand out: phase-locked-loop variations, masking circuits, and matched-filter circuits.
In the phase-locked-loop circuit variations, a voltage-controlled oscillator is synchronized with the clock frequency of the encoded data and used to provide a reference input to a phase comparator. The phase comparator detects phase shifts in the encoded data which provides a basis for decoding the data. An example of this technique is found in U.S. Pat. No. 4,167,760, "Bi-Phase Decoder Apparatus and Method," issued to D. G. Decker, Sept. 11, 1979.
In the masking method, significant transitions in the encoded waveform are used to trigger a multivibrator into a masking state which persists for a length of time sufficient to mask a succeeding nonsignificant transition in the encoded waveform.
Both the phase-locked-loop and masking circuit techniques rely for normal operation upon clear, sharp waveform transitions for triggering various circuit functions. Consequently, they are sensitive to distortions in the waveforms such as pulse-spreading and jitter.
The matched filter circuit approach utilizes a technique known as integrate-and-dump in which a matched filter with a rectangular impulse response is discharged just after its output peaks. Timing for such circuits is commonly provided by a voltage-controlled oscillator which is synchronized with the input data clock. As the input data clock increases in frequency the operational quality of these circuits declines. Synchronization becomes difficult and the time required for discharging begins to intrude upon the time available for integration. Consequently, matched filter decoders are limited in the frequency range over which they can operate.